2. DESIGN FLOW OVERVIEW 7
2.1 Design Levels 7
2.2 Top-down System Design 9
2.3 Bottom-up Verification 11
SIMULATION TOOLS IN SYSTEM DESIGN 15
3i Use of Simulation Tools within the Design Flow 15
3.2 Specific Simulation Algorithms of RF Simulators 17
33 Criteria of he Simulator Selection 21
3.4 nternet Resources for Simulation Tools 23
4. SYSTEM LEVEL MODELING 25
4. System Level Simulation 25
4.2 Simulation Technology of System Leel Simulators 26
4.3 Complex Baseband Simulation 27
4.3 1 Principle 27
4.3.2 Example for baseband simulation 30
4.33 Restrictions and advantages of baseband modeling 30
4.4 Mode1 Libraries for System Simulation 31
4.5 Creation of Own Primitive and Hierarchical Models 33
4.51 SPW modeling example 33
5. VFDL-AMS FOR BLOCK LEVEL SIMULATION 39
5I1 introduction 39
5.2 VHDL-AMS Standardization 40
5.3 A Simple Block Level Example - Analog PLL 41
5. .1 Mathematical models of basic blocks 42
5.1.2 Structural description of the PLL circuit in VHDL-AMS 44
5.3.3 VHDL-AMS description of basic blocks 47
5.4 Summary 50
6. INTRODLUTION TO VHDL-AMS 51
6. Aim of this Introduction 51
62 Repetition of Basics of VHIDL 1076-1993 52
6.21 Design units 52
6.2.2 Logical libraries and compilation of design units 56
6l.3 Concurrent statements 60
6.2.4 A simple pure digital example - divider 65
6.3 Conservative Systems Description 66
6.31 Network analysis problem 67
63.2 Nature, terminal and branch quantity declarations 71
6. .' Simultianeous statements and free quantity declarations 78
6.3.4 Example of a conservative system - A-law companding 85
6.3,5 Attributes in VHDL-AMS 88
6.36 Example - higher order lowpass filter 103
6.4 Description of Nonconservative Systems 105
6.5 Mixed-Sinal Simulation 107
6.5. Attributes for rixed-signal modeling 108
6.5.2 Mixed-signal simulation cycle 114
6.6 Analysis Domains 116
6. 1 Supported domains 116
i6. 2 S all-signal and noise domain simulation 118
6.7 Summary 124
7, SELLECTED RF BLOCKS IN VJHDL-AMS 127
7.1 Library Overview 127
7.2 Signal Sources 128
7.2. independent sources 128
7.2.2 Modulated sources 130
7.2.3 Wobble generator 133
72.4 Pseudorandom binary source 135
7.3 Basic RF Building Bl ks 137
7.3.1 Low-noise amplifier 37
7 3.2 Mixer 142
7.33 Charge pump 146
73.4 Analog VCO 150
7.3.5 Digital VCO 153
7.316 Filters 157
7.3.7 Switch 163
7.3.8 General n-bit AiD and D/A converter 164
7.3,9 Simple channel 169
7.4 Measurement and Observation Units 1 74
7.4.1 Peak detector 174
7.4.2 Frequency measurement unit 175
7.4.3 Power meter 178
7.5 Block Level Example of a Linear PLL 183
. MACRONMODELING IN VHDL-AMS 191
8.1 Introduction 1 91
8.2 General Methodology 191
8.3 Input and Output Stages 194
8.3 1 input stages 194
8.3.2 Output stages 197
8A4 OpAmp Macromodel 199
9. COMPLEX EXAMPLE: WLAN RECEIVER 203
9.1 Introduction 203
9.2 Example Specification 204
9.3 Example Modeling 207
9.4 Example Calibration 211
9.5 Example Verification 214
10. MODELING OF ANALOG BLOCKS IN VERILOG-A 219
10.1 introduction 219
10,2 Writing Custom Behavioral Models 220
10.2, Verilog-A principles 220
10,2,2 LNA mnodeling example 222
10,2.3 Creating a Verilog-A model 226
10.3 Overview of the Cadence Model Library rflib 231
10.4 Modeling and Simulation of a WLAN Receiver 236
10.4.1 WLAN receiver modeling using Cadence libraries 237
10,4.2 Simulation of the WLAN receiver 240
11. CHARACTERIZATION FOR BOTTOM-UP VERIFICATION 247
11.1 Concept of Characterization 247
11 2 RF Characteristics and Parameters 248
" 1.3 Application of Characterization 252
1 I 4 Example Characterization of an LNA 254
1 1.5 Characterization Environment 258
11.6 Characterization Using the OCEAN Script Language 262
11 .6 1 Creation of the testbench schematic 262
11.6.2 Analysis settings and simulation 263
11.63 Combination and extension of the OCEAN scripts 266
12. ADVANCED METHODS FOR OVERALL SYSTLM
SPEC F ICAT ION AND VALIDATION 271
12.1 Gap between System Level and Block Level Simulation 271
12. File Coupling of Simulators 272
12.3 Direct Cosimulation of System Level and Analog
Sirnlators 273
12.4 Generated Black Box Models 279