Digital systems testing and testable design = 数字系统测试和可测性设计 /
副标题：无
作 者：Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman.
分类号：
ISBN：9787302077473
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简介
Digital Systems Testing and Testable Design一书，是全美大学生和研究生优秀教材，比较系统地介绍了结构测试的理论和方法、可测性设计理论和度量方法、测试数据的处理及简化的理论和方法以及智能芯片(处理器、数字信号处理器和自动机等)测试理论和方法等。该书共有15章，分为3部分。前8章为第一部分，主要介绍数字系统、数字微系统芯片缺陷的来源、逻辑描述的方法——故障的建模、故障模拟、测试单固定故障、测试桥接故障、智能数字系统的功能测试及其范围等；第9章～第14章是第二部分，主要介绍数字系统的可测性设计理论和方法、建内自测试BIST测试数据压缩方法等现代测试理论和方法；第15章足第三部分，主要讨论系统测试的方法。该书概念清晰层次分明、定义和证明准确、算法推导和阐述简练。每章附有大量练习题可帮助读者对于概念的消化吸收。
目录
preface
how this book was written
1. introduction
2. modeling
2.1 basic concepts
2.2 functional modeling at the logic level
2.2.1 truth tables and primitive cubes
2.2.2 state tables and flow tables
2.2.3 binary decision diagrams
2.2.4 programs as functional models
2.3 functional modeling at the register level
2.3.1 basic rtl constructs
2.3.2 timing modeling in rtls
2.3.3 internal rtl models
2.4 structural models
2.4.1 external representation
2.4.2 structural properties
2.4.3 internal representation
2.4.4 wired logic and bidirectionality
.2.5 level of modeling
references
problems
3. logic simulation
3.1 applications
3.2 problems in simulation-based design verification
3.3 types of simulation
3.4 the unknown logic value
3.5 compiled simulation
3.6 event-driven simulation
3.7 delay models
3.7.1 delay modeling for gates
3.7.2 delay modeling for functional elements
3.7.3 delay modeling in rtls
3.7.4 other aspects of delay modeling
3.8 element evaluation
3.9 hazard detection
3.10 gate-level event-driven simulation
3.10.1 transition-independent nominal transport delays
3.10.2 other logic values
3.10.2.1 tristate logic
3.10.2.2 mos logic
3.10.3 other delay models
3.10.3.1 rise and fall delays
3.10.3.2 inertial delays
3.10.3.3 ambiguous delays
3.10.4 oscillation control
3.11 simulation engines
references
problems
4. fault modeling
4.1 logical fault models
4.2 fault detection and redundancy
4.2.1 combinational circuits
4.2.2 sequential circuits
4.3 fault equivalence and fault location
4.3.1 combinational circuits
4.3.2 sequential circuits
4.4 fault dominance
4.4.1 combinational circuits
4.4.2 sequential circuits
4.5 the single stuck-fault model
4.6 the multiple stuck-fault model
4.7 stuck rtl variables
4.8 fault variables
references
problems
5. fault simulation
5.1 applications
5.2 general fault simulation techniques
5.2.1 serial fault simulation
5.2.2 common concepts and terminology
5.2.3 parallel fault simulation
5.2.4 deductive fault simulation
5.2.4.1 two-valued deductive simulation
5.2.4.2 three-valued deductive simulation
5.2.5 concurrent fault simulation
5.2.6 comparison
5.3 fault simulation for combinational circuits
5.3.1 parallel-pattern single-fault propagation
5.3.2 critical path tracing
5.4 fault sampling
5.5 statistical fault analysis
5.6 concluding remarks
references
problems
6. testing for single stuck faults
6.1 basic issues
6.2 atg for ssfs in combinational circuits
6.2.1 fault-oriented atg
6.2.1.1 common concepts
6.2.1.2 algorithms
6.2.1.3 selection criteria
6.2.2 fault-independent atg
6.2.3 random test generation
6.2.3.1 the quality of a random test
6.2.3.2 the length of a random test
6.2.3.3 determining detection probabilities
6.2.3.4 rtg with nonuniform distributions
6.2.4 combined deterministic/random tg
6.2.5 atg systems
6.2.6 other tg methods
6.3 atg for ssfs in sequential circuits
6.3.1 tg using iterative array models
6.3.2 simulation-based tg
6.3.3 tg using rtl models
6.3.3.1 extensions of the d-algorithm
6.3.3.2 heuristic state-space search
6.3.4 random test generation
6.4 concluding remarks
references
problems
7. testing for bridging faults
7.1 the bridging-fault model
7.2 detection of nonfeedback bridging faults
7.3 detection of feedback bridging faults
7.4 bridging faults simulation
7.5 test generation for bridging faults
7.6 concluding remarks
references
problems
8. functional testing
8.1 basic issues
8.2 functional testing without fault models
8.2.1 heuristic methods
8.2.2 functional testing with binary decision diagrams
8.3 exhaustive and pseudoexhaustive testing
8.3.1 combinational circuits
8.3.1.1 partial-dependence circuits
8.3.1.2 partitioning techniques
8.3.2 sequential circuits
8.3.3 iterative logic arrays
8.4 functional testing with specific fault models
8.4.1 functional fault models
8.4.2 fault models for microprocessors
8.4.2.1 fault model for the register-decoding function
8.4.2.2 fault model for the instruction-decoding and instruction-sequencing function
8.4.2.3 fault model for the data-storage function
8.4.2.4 fault model for the data-transfer function
8.4.2.5 fault model for the data-manipulation function
8.4.3 test generation procedures
8.4.3.1 testing the register-decoding function
8.4.3.2 testing the instruction-decoding and instruction-sequencing function
8.4.3.3 testing the data-storage and data-transfer functions
8.4.4 a casestudy
8.5 concluding remarks
references
problems
9. design for testability
9.1 testability
9.1.1 trade-offs
9.1.2 controllability and observability
9.2 ad hoc design for testability techniques
9.2.1 test points
9.2.2 initialization
9.2.3 monostable multivibrators
9.2.4 oscillators and clocks
9.2.5 partitioning counters and shift registers
9.2.6 partitioning of large combinational circuits
9.2.7 logical redundancy
9.2.8 global feedback paths
9.3 controllability and observability by means of scan registers
9.3.1 generic boundary scan
9.4 generic scan-based designs
9.4.1 full serial integrated scan
9.4.2 isolated serial scan
9.4.3 nonserial scan
9.5 storage cells for scan designs
9.6 classical scan designs
9.7 scan design costs
9.8 board-level and system-level dft approaches
9.8.1 system-level busses
9.8.2 system-level scan paths
9.9 some advanced scan concepts
9.9.1 multiple test session
9.9.2 partial scan using i-paths
9.9.3 ballast -- a structured partial scan design
9.10 boundary scan standards
9.10.1 background
9.10.2 boundary scan cell
9.10.3 board and chip test modes
9.10.4 the test bus
9.10.5 test bus circuitry
9.10.5.1 the tap controller
9.10.5.2 registers
references
problems
10. compression techniques
10.1 general aspects of compression techniques
10.2 ones-count compression
10.3 transition-count compression
10.4 parity-check compression
10.5 syndrome testing
10.6 signature analysis
10.6.1 theory and operation of linear feedback shift registers
10.6.2 lfsrs used as signature analyzers
10.6.3 multiple-input signature registers
10.7 concluding remarks
references
problems
11. built-in self-test
11.1 introduction to bist concepts
11.1.1 hardcore
11.1.2 levels of test
11.2 test-pattern generation for bist
11.2.1 exhaustive testing
11.2.2 pseudorandom testing
11.2.3 pseudoexhaustive testing
11.2.3.1 logical segmentation
11.2.3.2 constant-weight patterns
11.2.3.3 identification of test signal inputs
11.2.3.4 test pattern generators for pseudoexhaustive tests
11.2.3.5 physical segmentation
11.3 generic off-line bist architectures
11.4 specific bist architectures
11.4.1 a centralized and separate board-level bist architecture (csbl)
11.4.2 built-in evaluation and self-test (best)
11.4.3 random-test socket (rts)
11.4.4 lssd on-chip self-test (locst)
11.4.5 self-testing using misr and parallel srsg (stumps)
11.4.6 a concurrent bist architecture (cbist)
11.4.7 a centralized and embedded bist architecture with boundary scan (cebs)
11.4.8 random test data (rtd)
11.4.9 simultaneous self-test (sst)
11.4.10 cyclic analysis testing system (cats)
11.4.11 circular self-test path (cstp)
11.4.12 built-in logic-block observation (bilbo)
11.4.12.1 case study
11.4.13 summary
11.5 some advanced bist concepts
11.5.1 test schedules
11.5.2 control of bilbo registers
11.5.3 partial-intrusion bist
11.6 design for self-test at board level
references
problems
12. logic-level diagnosis
12.1 basic concepts
12.2 fault dictionary
12.3 guided-probe testing
12.4 diagnosis by uut reduction
12.5 fault diagnosis for combinational circuits
12.6 expert systems for diagnosis
12.7 effect-cause analysis
12.8 diagnostic reasoning based on structure and behavior
references
problems
13. self-checking design
13.1 basic concepts
13.2 application of error-detecting and error-correcting codes
13.3 multiple-bit errors
13.4 checking circuits and self-checking
13.5 self-checking checkers
13.6 parity-check function
13.7 totally self-checking m/n code checkers
13.8 totally self-checking equality checkers
13.9 self-checking berger code checkers
13.10 toward a general theory of self-checking combinational circuits
13.11 self-checking sequential circuits
references
problems
14. pla testing
14.1 introduction
14.2 pla testing problems
14.2.1 fault models
14.2.2 problems with traditional test generation methods
14.3 test generation algorithms for plas
14.3.1 deterministic test generation
14.3.2 semirandom test generation
14.4 testable pla designs
14.4.1 concurrent testable plas with special coding
14.4.1.1 pla with concurrent error detection by a series of checkers
14.4.1.2 concurrent testable plas using modified berger code
14.4.2 parity testable plas
14.4.2.1 pla with universal test set
14.4.2.2 autonomously testable plas
14.4.2.3 a built-in self-testable pla design with cumulative parity comparison
14.4.3 signature-testable plas
14.4.3.1 pla with multiple signature analyzers
14.4.3.2 self-testable plas with single signature analyzer
14.4.4 partioning and testing of plas
14.4.4.1 pla with bilbos
14.4.4.2 parallel-testable plas
14.4.4.3 divide-and-conquer strategy for testable pla design
14.4.5 fully-testable pla designs
14.5 evaluation of pla test methodologies
14.5.1 measures of tdms
14.5.1.1 resulting effect on the original design
14.5.1.2 requirements on test environment
14.5.2 evaluation of pla test techniques
references
problems
15. system-level diagnosis
15.1 a simple model of system-level diagnosis
15.2 generalizations of the pmc model
15.2.1 generalizations of the system diagnostic graph
15.2.2 generalization of possible test outcomes
15.2.3 generalization of diagnosability measures
references
problems
index
how this book was written
1. introduction
2. modeling
2.1 basic concepts
2.2 functional modeling at the logic level
2.2.1 truth tables and primitive cubes
2.2.2 state tables and flow tables
2.2.3 binary decision diagrams
2.2.4 programs as functional models
2.3 functional modeling at the register level
2.3.1 basic rtl constructs
2.3.2 timing modeling in rtls
2.3.3 internal rtl models
2.4 structural models
2.4.1 external representation
2.4.2 structural properties
2.4.3 internal representation
2.4.4 wired logic and bidirectionality
.2.5 level of modeling
references
problems
3. logic simulation
3.1 applications
3.2 problems in simulation-based design verification
3.3 types of simulation
3.4 the unknown logic value
3.5 compiled simulation
3.6 event-driven simulation
3.7 delay models
3.7.1 delay modeling for gates
3.7.2 delay modeling for functional elements
3.7.3 delay modeling in rtls
3.7.4 other aspects of delay modeling
3.8 element evaluation
3.9 hazard detection
3.10 gate-level event-driven simulation
3.10.1 transition-independent nominal transport delays
3.10.2 other logic values
3.10.2.1 tristate logic
3.10.2.2 mos logic
3.10.3 other delay models
3.10.3.1 rise and fall delays
3.10.3.2 inertial delays
3.10.3.3 ambiguous delays
3.10.4 oscillation control
3.11 simulation engines
references
problems
4. fault modeling
4.1 logical fault models
4.2 fault detection and redundancy
4.2.1 combinational circuits
4.2.2 sequential circuits
4.3 fault equivalence and fault location
4.3.1 combinational circuits
4.3.2 sequential circuits
4.4 fault dominance
4.4.1 combinational circuits
4.4.2 sequential circuits
4.5 the single stuck-fault model
4.6 the multiple stuck-fault model
4.7 stuck rtl variables
4.8 fault variables
references
problems
5. fault simulation
5.1 applications
5.2 general fault simulation techniques
5.2.1 serial fault simulation
5.2.2 common concepts and terminology
5.2.3 parallel fault simulation
5.2.4 deductive fault simulation
5.2.4.1 two-valued deductive simulation
5.2.4.2 three-valued deductive simulation
5.2.5 concurrent fault simulation
5.2.6 comparison
5.3 fault simulation for combinational circuits
5.3.1 parallel-pattern single-fault propagation
5.3.2 critical path tracing
5.4 fault sampling
5.5 statistical fault analysis
5.6 concluding remarks
references
problems
6. testing for single stuck faults
6.1 basic issues
6.2 atg for ssfs in combinational circuits
6.2.1 fault-oriented atg
6.2.1.1 common concepts
6.2.1.2 algorithms
6.2.1.3 selection criteria
6.2.2 fault-independent atg
6.2.3 random test generation
6.2.3.1 the quality of a random test
6.2.3.2 the length of a random test
6.2.3.3 determining detection probabilities
6.2.3.4 rtg with nonuniform distributions
6.2.4 combined deterministic/random tg
6.2.5 atg systems
6.2.6 other tg methods
6.3 atg for ssfs in sequential circuits
6.3.1 tg using iterative array models
6.3.2 simulation-based tg
6.3.3 tg using rtl models
6.3.3.1 extensions of the d-algorithm
6.3.3.2 heuristic state-space search
6.3.4 random test generation
6.4 concluding remarks
references
problems
7. testing for bridging faults
7.1 the bridging-fault model
7.2 detection of nonfeedback bridging faults
7.3 detection of feedback bridging faults
7.4 bridging faults simulation
7.5 test generation for bridging faults
7.6 concluding remarks
references
problems
8. functional testing
8.1 basic issues
8.2 functional testing without fault models
8.2.1 heuristic methods
8.2.2 functional testing with binary decision diagrams
8.3 exhaustive and pseudoexhaustive testing
8.3.1 combinational circuits
8.3.1.1 partial-dependence circuits
8.3.1.2 partitioning techniques
8.3.2 sequential circuits
8.3.3 iterative logic arrays
8.4 functional testing with specific fault models
8.4.1 functional fault models
8.4.2 fault models for microprocessors
8.4.2.1 fault model for the register-decoding function
8.4.2.2 fault model for the instruction-decoding and instruction-sequencing function
8.4.2.3 fault model for the data-storage function
8.4.2.4 fault model for the data-transfer function
8.4.2.5 fault model for the data-manipulation function
8.4.3 test generation procedures
8.4.3.1 testing the register-decoding function
8.4.3.2 testing the instruction-decoding and instruction-sequencing function
8.4.3.3 testing the data-storage and data-transfer functions
8.4.4 a casestudy
8.5 concluding remarks
references
problems
9. design for testability
9.1 testability
9.1.1 trade-offs
9.1.2 controllability and observability
9.2 ad hoc design for testability techniques
9.2.1 test points
9.2.2 initialization
9.2.3 monostable multivibrators
9.2.4 oscillators and clocks
9.2.5 partitioning counters and shift registers
9.2.6 partitioning of large combinational circuits
9.2.7 logical redundancy
9.2.8 global feedback paths
9.3 controllability and observability by means of scan registers
9.3.1 generic boundary scan
9.4 generic scan-based designs
9.4.1 full serial integrated scan
9.4.2 isolated serial scan
9.4.3 nonserial scan
9.5 storage cells for scan designs
9.6 classical scan designs
9.7 scan design costs
9.8 board-level and system-level dft approaches
9.8.1 system-level busses
9.8.2 system-level scan paths
9.9 some advanced scan concepts
9.9.1 multiple test session
9.9.2 partial scan using i-paths
9.9.3 ballast -- a structured partial scan design
9.10 boundary scan standards
9.10.1 background
9.10.2 boundary scan cell
9.10.3 board and chip test modes
9.10.4 the test bus
9.10.5 test bus circuitry
9.10.5.1 the tap controller
9.10.5.2 registers
references
problems
10. compression techniques
10.1 general aspects of compression techniques
10.2 ones-count compression
10.3 transition-count compression
10.4 parity-check compression
10.5 syndrome testing
10.6 signature analysis
10.6.1 theory and operation of linear feedback shift registers
10.6.2 lfsrs used as signature analyzers
10.6.3 multiple-input signature registers
10.7 concluding remarks
references
problems
11. built-in self-test
11.1 introduction to bist concepts
11.1.1 hardcore
11.1.2 levels of test
11.2 test-pattern generation for bist
11.2.1 exhaustive testing
11.2.2 pseudorandom testing
11.2.3 pseudoexhaustive testing
11.2.3.1 logical segmentation
11.2.3.2 constant-weight patterns
11.2.3.3 identification of test signal inputs
11.2.3.4 test pattern generators for pseudoexhaustive tests
11.2.3.5 physical segmentation
11.3 generic off-line bist architectures
11.4 specific bist architectures
11.4.1 a centralized and separate board-level bist architecture (csbl)
11.4.2 built-in evaluation and self-test (best)
11.4.3 random-test socket (rts)
11.4.4 lssd on-chip self-test (locst)
11.4.5 self-testing using misr and parallel srsg (stumps)
11.4.6 a concurrent bist architecture (cbist)
11.4.7 a centralized and embedded bist architecture with boundary scan (cebs)
11.4.8 random test data (rtd)
11.4.9 simultaneous self-test (sst)
11.4.10 cyclic analysis testing system (cats)
11.4.11 circular self-test path (cstp)
11.4.12 built-in logic-block observation (bilbo)
11.4.12.1 case study
11.4.13 summary
11.5 some advanced bist concepts
11.5.1 test schedules
11.5.2 control of bilbo registers
11.5.3 partial-intrusion bist
11.6 design for self-test at board level
references
problems
12. logic-level diagnosis
12.1 basic concepts
12.2 fault dictionary
12.3 guided-probe testing
12.4 diagnosis by uut reduction
12.5 fault diagnosis for combinational circuits
12.6 expert systems for diagnosis
12.7 effect-cause analysis
12.8 diagnostic reasoning based on structure and behavior
references
problems
13. self-checking design
13.1 basic concepts
13.2 application of error-detecting and error-correcting codes
13.3 multiple-bit errors
13.4 checking circuits and self-checking
13.5 self-checking checkers
13.6 parity-check function
13.7 totally self-checking m/n code checkers
13.8 totally self-checking equality checkers
13.9 self-checking berger code checkers
13.10 toward a general theory of self-checking combinational circuits
13.11 self-checking sequential circuits
references
problems
14. pla testing
14.1 introduction
14.2 pla testing problems
14.2.1 fault models
14.2.2 problems with traditional test generation methods
14.3 test generation algorithms for plas
14.3.1 deterministic test generation
14.3.2 semirandom test generation
14.4 testable pla designs
14.4.1 concurrent testable plas with special coding
14.4.1.1 pla with concurrent error detection by a series of checkers
14.4.1.2 concurrent testable plas using modified berger code
14.4.2 parity testable plas
14.4.2.1 pla with universal test set
14.4.2.2 autonomously testable plas
14.4.2.3 a built-in self-testable pla design with cumulative parity comparison
14.4.3 signature-testable plas
14.4.3.1 pla with multiple signature analyzers
14.4.3.2 self-testable plas with single signature analyzer
14.4.4 partioning and testing of plas
14.4.4.1 pla with bilbos
14.4.4.2 parallel-testable plas
14.4.4.3 divide-and-conquer strategy for testable pla design
14.4.5 fully-testable pla designs
14.5 evaluation of pla test methodologies
14.5.1 measures of tdms
14.5.1.1 resulting effect on the original design
14.5.1.2 requirements on test environment
14.5.2 evaluation of pla test techniques
references
problems
15. system-level diagnosis
15.1 a simple model of system-level diagnosis
15.2 generalizations of the pmc model
15.2.1 generalizations of the system diagnostic graph
15.2.2 generalization of possible test outcomes
15.2.3 generalization of diagnosability measures
references
problems
index
Digital systems testing and testable design = 数字系统测试和可测性设计 /
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