Logic and computer design fundamentals = 数字逻辑与计算机硬件设计基础 / 2nd ed. updated.
副标题：无
作 者：M. Morris Mano, Charles R. Kime.
分类号：
ISBN：9787505376625
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简介
本书是计算机科学、计算机工程和电气工程等专业的学生学习逻辑电路设计的入门教程。全
书共7章和一个附录，前4章介绍数制、开关代数、真值表和卡诺图，并讲解了逻辑函数的化
简以及组合系统的分析与设计；后3章介绍时序系统的分析与设计、移位寄存器和计数器、
可编
程逻辑器件、用列表法和状态分割法进行状态化简和状态分配；附录部分介绍了4个实验操
作平台及25个实验室作业。
要学好逻辑电路设计这门课程，需要掌握好三个环节：理论、习题和实验。本书紧紧抓住这
些教学环节，系统地阐述了逻辑设计的核心内容，尤其突出了系统的分析和设计方法。对于
需要学生通过练习进一步巩固的重点内容，书中均布置了适量作业。在每章讲述内容之后专
门安排了一节解题实例和一节习题。本书是学习逻辑电路设计难得的一本好教材，既可作为
计算机、电气工程和通信、电子等专业学生的教材或教学参考书，也可供相关专业工程技术
人员参考。更多>>
目录
chapter 1 3
digltal computers and information
1-1 digital computers
information representation
computer structure
more on the generic computer
1-2 number systems
binary numbers
octal and hexadecimal numbers
number ranges
1-3 arithmetic operations
conversion from decimal to other bases
1-4 decimal codes
bcd addition
1-5 alphanumeric codes
ascii character code
parity bit
1-6 chapter sununary
references
problems
.chapter 2 27
combinational logic circuits
2-1 binary logic and gates
binary logic
logic gates
2-2 boolean algebra
basic identities of boolean algebra
algebraic manipulation
complement of a function
2-3 standard forms
minterms and maxterms
sum of products
product of sums
2-4 map simplification
two-variable map
me-variable map
four-variable map
2-5 map manipulation
essential prime implicants
nonessential prime implicants
product-of sums simplification
don't--care condihons
2-6 nand and nor gates
nand circuits
two-level implementation
multi1evel nand circuits
nor circuits
2-7 exclusive-or gates
odd function
parity generation and checking
2-8 integrated circuits
levels of integration
digital logic families
positive and negative logic
transmission gates
2-9 chapter sununary
references
problems
chapter 3
combinational logic design
3-1 combinational circuits
3-2 design topics
design hierarchy
top-down design
computer-aided design
hardware description languages
logic synthesis
3-3 analysis procedure
derivation of boolean functions
derivation of the truth table
logic simulation
3-4 design procedure
code converters
3-5 decoders
decoder expansion
combinahonal circuit implemenation
3-6 enceders
priority encoder
3-7 multiplexers
combinahonal circuit implementation
demultiplexer
3-8 binare adders
half adder
full adder
binare ripple carry adder
cap lookahead aduer
3-9 binary subtraction
complements
subtraction with complements
3-10 binary adder-subtractors
signed binary numbers
signed binary addition and subtraction
overflow
3-11 binny multipliers
3-12 decimal arithmetic
use of complements in decimal
3-13 hdl representations -- vhdl
structural description
dataflow description
hierarchical description
behavioral description
3-14 hdl representations - verilog
structural description
dataflow description
hierarchical description
behavioral description
3-15 chapter sununary
references
problems
chapter 4 183
sequential circuits
4-1 sequential circuit definitions
4-2 latches
sr and s r latches
d latch
4-3 flip-flops
master-slave flip-flop
edge-triggered flip-flop
standard graphics symbols
characteristic tables
direct inputs
4-4 sequential circuit analysis
input equations
state table
analysis with jk flip-flops
state diagram
4-5 sequential circuit design
design procedure
finding state diagrams and state tables
4-6 designing with d flip-flops
designing with unused states
4-7 designing with jk flip-flops
flip-flop excitation tables
design procedure
4-8 hdl representation for sequential circuits -- vhdl
4-9 hdl representation for sequential circuits -- verilog
4-10 references
problems
chapter 5 249
registers and coljnters
5-1 definition of register and counter
5-2 registers
register with parallel load
5-3 shift registers
serial transfer
serial addition
shift register with parallel load
bidirectional shift register
5-4 ripple counter
5-5 synchronous binary counters
design of binary counters
counter with d flip-flops
serial and parallel counters
up-down binary counter
binary counter with parallel load
5-6 other counters
bcd counter
arbitrary count sequence
5-7 hdl representation for shift registers and counters
5-8 hdl representation for shift registers and counters
5-9 chapter sununary
references
problems
chapter 6 285
memory and programmable logic devices
6-1 memory and progranunable logic device
definitions
6-2 random-access memory
write and read operations
timing waveforms
properties of memory
6-3 ram integrated circuits
three-state buffers
coincident selection
dynamic ram ics
6-4 array of ram ics
arrays of dynamic ram ics
6-5 programmable logic technologies
6-6 read--only memory
combinational circuit implementation
6-7 programmable logic array
6-8 programmable array logic devices
6-9 vlsi programmable logic devices
altera max 7000 cplds
xilinx xc4000 structure
xilinx interconnections
xilinx logic
6-10 chapter sununary
references
problems
chapter 7 339
register transfers and datapaths
7-1 datapaths and operations
7-2 register transfer operations
a note for vhdl and verilog users only
7-3 microoperations
arithmetic microoperations
logic microoperations
shift microoperations
7-4 multiplexer-based transfer
7-5 bus-based transfer
three-state bus
memory transfer
7-6 datapaths
7-7 the arithmetic/logic unit
anthmetic circuit
logic circuit
arithmetic/logic unit
7-8 the shifter
barrel shifter
7-9 datapath representation
7-10 the control word
7-11 pipelined datapath
execution of pipeline microoperations
7-12 chapter sununary
references
problems
chapter 8 391
sequencing and contol
8-1 the control unit
8-2 algorithmic state machines
the asm chart
timing considerations
8-3 design example: binary multiplier
binary multiplier
multiplier datapath
asm chart for multiplier
8-4 hardwired control
sequence register and decoder
one flip-flop per state
8-5 hdl representation of the binary multiplier - vhdl
8-6 hdl representation of the binary multiplier - verilog
8-7 microprogranund control
binary multiplier example
8-8 a simple computer architecture
instructions
instruction formats
storage resource diagram
8-9 single-cycle hardwired control
instruction decoder
sample instructions and program
8-10 multiple-cycle microprogranund control
microprogram design
the hardwired alternative
8-11 pipelined control
pipeline programming and performance
8-12 chapter summary
references
problems
chapter 9 467
instruction set architecture
9-1 computer architecture concepts
basic computer operation cycle
register set
9-2 operand addressing
three-address instructions
two-address insmictions
one-address instructions
zero-address instructions
addressing architectures
9-3 addressing modes
implied mode
inundiate mode
register and register-indirect modes
direct addressing mode
indirect addressing mode
relative addressing mode
indexed addressing mode
summary of addressing modes
9-4 insmiction set architectures
9-5 data transfer instructions
stack instructions
independent versus memory-mapped i/o
9-6 data manipulation instructions
arithmetic instructions
logical and bit manipulation instructions
shift instructions
9-7 floating-point computations
arithmetic operations
biased exponent
standard operand format
9-8 program control instructions
conditional branch instructions
procedure call and return instructions
9-9 program interrupt
types of interrupts
processing external interrupts
9-10 chapter sununary
references
problems
chapter l0 511
central processing unit designs
10-1 two cpu designs
10-2 the complex instruction set computer
insmiction set aichitecture
datapath organization
microprogranuned control organization
microprograrn structure
microroutines
10-3 the reduced instruction set computer
instruction set architecture
addressing modes
datapath organization
control organization
data hazards
control hazards
10-4 more on design
cisc-risc comparison
high-performance cpu concepts
recent architectural innovations
digital systems
10-5 chapter summary
references
problems
chapter ll 575
input-output and communication
11-1 computer llo
11-2 sample peripherals
keyboard
hard disk
gmphics display
i/o transfer rates
11-3 i/o interfaces
i/o bus and interface unit
example of i/o interface
strobing
handshaking
11-4 serial communicahon
asynchronous transmission
synchronous transmission
the keyboard revisited
a packet-based serial i/o bus
11-5 modes of transfer
example of program-controlled thosfer
interrupt-initiated transfer
11-6 priority interrupt
daisy chain priority
parallel priority hardware
11-7 direct memory access
dma controller
dma transfer
11-8 i/o processors
11-9 chapter summary
references
prob1ems
chapter l2 613
memor systems
12-1 memory hierarchy
12-2 locality of reference
12-3 cache memory
cache mappings
line size
cache loading
write methods
integration of concepts
instruction and data caches
multiple-level caches
12-4 virtual memory
page tables
translation lookaside buffer
vinual memory and cache
12-5 chapter sununary
references
problems
index 643
digltal computers and information
1-1 digital computers
information representation
computer structure
more on the generic computer
1-2 number systems
binary numbers
octal and hexadecimal numbers
number ranges
1-3 arithmetic operations
conversion from decimal to other bases
1-4 decimal codes
bcd addition
1-5 alphanumeric codes
ascii character code
parity bit
1-6 chapter sununary
references
problems
.chapter 2 27
combinational logic circuits
2-1 binary logic and gates
binary logic
logic gates
2-2 boolean algebra
basic identities of boolean algebra
algebraic manipulation
complement of a function
2-3 standard forms
minterms and maxterms
sum of products
product of sums
2-4 map simplification
two-variable map
me-variable map
four-variable map
2-5 map manipulation
essential prime implicants
nonessential prime implicants
product-of sums simplification
don't--care condihons
2-6 nand and nor gates
nand circuits
two-level implementation
multi1evel nand circuits
nor circuits
2-7 exclusive-or gates
odd function
parity generation and checking
2-8 integrated circuits
levels of integration
digital logic families
positive and negative logic
transmission gates
2-9 chapter sununary
references
problems
chapter 3
combinational logic design
3-1 combinational circuits
3-2 design topics
design hierarchy
top-down design
computer-aided design
hardware description languages
logic synthesis
3-3 analysis procedure
derivation of boolean functions
derivation of the truth table
logic simulation
3-4 design procedure
code converters
3-5 decoders
decoder expansion
combinahonal circuit implemenation
3-6 enceders
priority encoder
3-7 multiplexers
combinahonal circuit implementation
demultiplexer
3-8 binare adders
half adder
full adder
binare ripple carry adder
cap lookahead aduer
3-9 binary subtraction
complements
subtraction with complements
3-10 binary adder-subtractors
signed binary numbers
signed binary addition and subtraction
overflow
3-11 binny multipliers
3-12 decimal arithmetic
use of complements in decimal
3-13 hdl representations -- vhdl
structural description
dataflow description
hierarchical description
behavioral description
3-14 hdl representations - verilog
structural description
dataflow description
hierarchical description
behavioral description
3-15 chapter sununary
references
problems
chapter 4 183
sequential circuits
4-1 sequential circuit definitions
4-2 latches
sr and s r latches
d latch
4-3 flip-flops
master-slave flip-flop
edge-triggered flip-flop
standard graphics symbols
characteristic tables
direct inputs
4-4 sequential circuit analysis
input equations
state table
analysis with jk flip-flops
state diagram
4-5 sequential circuit design
design procedure
finding state diagrams and state tables
4-6 designing with d flip-flops
designing with unused states
4-7 designing with jk flip-flops
flip-flop excitation tables
design procedure
4-8 hdl representation for sequential circuits -- vhdl
4-9 hdl representation for sequential circuits -- verilog
4-10 references
problems
chapter 5 249
registers and coljnters
5-1 definition of register and counter
5-2 registers
register with parallel load
5-3 shift registers
serial transfer
serial addition
shift register with parallel load
bidirectional shift register
5-4 ripple counter
5-5 synchronous binary counters
design of binary counters
counter with d flip-flops
serial and parallel counters
up-down binary counter
binary counter with parallel load
5-6 other counters
bcd counter
arbitrary count sequence
5-7 hdl representation for shift registers and counters
5-8 hdl representation for shift registers and counters
5-9 chapter sununary
references
problems
chapter 6 285
memory and programmable logic devices
6-1 memory and progranunable logic device
definitions
6-2 random-access memory
write and read operations
timing waveforms
properties of memory
6-3 ram integrated circuits
three-state buffers
coincident selection
dynamic ram ics
6-4 array of ram ics
arrays of dynamic ram ics
6-5 programmable logic technologies
6-6 read--only memory
combinational circuit implementation
6-7 programmable logic array
6-8 programmable array logic devices
6-9 vlsi programmable logic devices
altera max 7000 cplds
xilinx xc4000 structure
xilinx interconnections
xilinx logic
6-10 chapter sununary
references
problems
chapter 7 339
register transfers and datapaths
7-1 datapaths and operations
7-2 register transfer operations
a note for vhdl and verilog users only
7-3 microoperations
arithmetic microoperations
logic microoperations
shift microoperations
7-4 multiplexer-based transfer
7-5 bus-based transfer
three-state bus
memory transfer
7-6 datapaths
7-7 the arithmetic/logic unit
anthmetic circuit
logic circuit
arithmetic/logic unit
7-8 the shifter
barrel shifter
7-9 datapath representation
7-10 the control word
7-11 pipelined datapath
execution of pipeline microoperations
7-12 chapter sununary
references
problems
chapter 8 391
sequencing and contol
8-1 the control unit
8-2 algorithmic state machines
the asm chart
timing considerations
8-3 design example: binary multiplier
binary multiplier
multiplier datapath
asm chart for multiplier
8-4 hardwired control
sequence register and decoder
one flip-flop per state
8-5 hdl representation of the binary multiplier - vhdl
8-6 hdl representation of the binary multiplier - verilog
8-7 microprogranund control
binary multiplier example
8-8 a simple computer architecture
instructions
instruction formats
storage resource diagram
8-9 single-cycle hardwired control
instruction decoder
sample instructions and program
8-10 multiple-cycle microprogranund control
microprogram design
the hardwired alternative
8-11 pipelined control
pipeline programming and performance
8-12 chapter summary
references
problems
chapter 9 467
instruction set architecture
9-1 computer architecture concepts
basic computer operation cycle
register set
9-2 operand addressing
three-address instructions
two-address insmictions
one-address instructions
zero-address instructions
addressing architectures
9-3 addressing modes
implied mode
inundiate mode
register and register-indirect modes
direct addressing mode
indirect addressing mode
relative addressing mode
indexed addressing mode
summary of addressing modes
9-4 insmiction set architectures
9-5 data transfer instructions
stack instructions
independent versus memory-mapped i/o
9-6 data manipulation instructions
arithmetic instructions
logical and bit manipulation instructions
shift instructions
9-7 floating-point computations
arithmetic operations
biased exponent
standard operand format
9-8 program control instructions
conditional branch instructions
procedure call and return instructions
9-9 program interrupt
types of interrupts
processing external interrupts
9-10 chapter sununary
references
problems
chapter l0 511
central processing unit designs
10-1 two cpu designs
10-2 the complex instruction set computer
insmiction set aichitecture
datapath organization
microprogranuned control organization
microprograrn structure
microroutines
10-3 the reduced instruction set computer
instruction set architecture
addressing modes
datapath organization
control organization
data hazards
control hazards
10-4 more on design
cisc-risc comparison
high-performance cpu concepts
recent architectural innovations
digital systems
10-5 chapter summary
references
problems
chapter ll 575
input-output and communication
11-1 computer llo
11-2 sample peripherals
keyboard
hard disk
gmphics display
i/o transfer rates
11-3 i/o interfaces
i/o bus and interface unit
example of i/o interface
strobing
handshaking
11-4 serial communicahon
asynchronous transmission
synchronous transmission
the keyboard revisited
a packet-based serial i/o bus
11-5 modes of transfer
example of program-controlled thosfer
interrupt-initiated transfer
11-6 priority interrupt
daisy chain priority
parallel priority hardware
11-7 direct memory access
dma controller
dma transfer
11-8 i/o processors
11-9 chapter summary
references
prob1ems
chapter l2 613
memor systems
12-1 memory hierarchy
12-2 locality of reference
12-3 cache memory
cache mappings
line size
cache loading
write methods
integration of concepts
instruction and data caches
multiple-level caches
12-4 virtual memory
page tables
translation lookaside buffer
vinual memory and cache
12-5 chapter sununary
references
problems
index 643
Logic and computer design fundamentals = 数字逻辑与计算机硬件设计基础 / 2nd ed. updated.
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