Application-Specific Integrated Circuits
副标题：无
作 者：(美)Michael John Sebastian Smith著
分类号：
ISBN：9787505384071
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简介
本书是一本有关专用集成电路（ASIC）的综合性和权威性书籍。书中叙述了VLSI系统设计的最新方法。利用商业化工具以及预先设计好的单元库已使得ASIC设计成为速度最快、成本最低而且错误最少的一种IC设计方法，因而ASIC和ASIC设计方法已迅速在工业界的各个应用领域得到推广。
本书介绍了半定制和可编程的ASIC。在对每种ASIC类型的数字逻辑设计与物理特性的基本原理进行描述后，讨论了ASIC逻辑设计——设计输入、逻辑综合、仿真以及测试，并进一步讲述了相应的物理设计——划分、平面布图规划、布局以及布线。此外，本书对在ASIC设计中需要了解的各方面知识以及必需的工作都有详尽叙述。
本书可作为大学高年级和研究生教材，也是ASIC领域工程技术人员的理想参考书。
目录
1 introduction to asics 1
1 .1 types of asics 4
1 .2 design flow 16
1 .3 case study 18
1 .4 economics of asics 20
1 .5 asic cell libraries 27
1 .6 summary 30
1 .7 problems 31
1 .8 bibliography 36
1 .9 references 38
2 cmos logic 39
2.1 cmos transistors 41
2.2 the cmos process 49
2.3 cmos design rules 58
2.4 combinational logic cells 60
2.5 sequential logic cells 70
2.6 datapath logic cells 75
2.7 i/o cells 99
2.8 cell compilers 102
2.9 summary 102
. 2.10 problems 103
2.11 bibliography 113
2.12 references 1 14
3 asic library design 117
3.1 transistors as resistors 117
3.2 transistor parasitic capacitance 122
3.3 logical effort 129
9.4 library-cell design 141
9.5 library architecture 142
3.6 gate-array design 144
3.7 standard-cell design 150
3.8 datapath-cell design 152
3.9 summary 155
3.10 problems 155
3.11 bibliography 187
3.12 references 168
4 programmable asics 169
4.1 the antifuse 170
4.2 static ram 1 74
4.3 eprom and eeprom technology 174
4.4 praaical isues 1 7e
4.5 specifications 1 7b
4.6 prep benchmarks 1 79
4.7 fpga economics 1 80
4.8 summary 184
4.9 problems 185
4.10 bibliography 190
4.11 references 190
5 programmable asic
logic cells 191
5.1 actel act 191
5.2 xilinx lca 204
5.3 altera flex 209
5.4 altera max 209
5.5 summary 218
5.6 problems 224
5.7 bibliography 229
5.8 references 230
6 programmable
asic i/o cells 231
6.1 dc output 292
6.2 ac output 295
8.9 dc input 243
6.4 ac input 24b
6.5 clock input 253
6.6 power input 255
6.7 xilinx i/o block 258
6.8 other i/o cells 261
6.9 summary 262
e.10 problems 269
6.11 bibliography 272
6.12 references 273
7 programmable
asic interconnect 275
7.1 aael act 275
7.2 xilinx lca 284
7.s xilinx epld 288
7.4 altera max 5000 and 7000 289
7.5 altera max 9000 290
7.6 altera flex 291
7.7 summary 292
7.8 problems 294
7.9 bibliography 297
7.10 references 297
8 programmable
asic design software 299
8.1 desian svstems 299
8.2 logic synthesis 3o4
8.3 the halfgate asic 307
8.4 summary 316
8.5 probiems 316
8.6 bibliography 320
8.7 references 326
9 low-level
design entry 327
9.1 schematic entry 328
9.2 low-level design languages 345
9.3 pla tools 353
9.4 edif 355
9.5 cfi design representation 969
9.6 summary 373
9.7 problems 373
9.8 bibliography 376
9.9 references 377
10 vhdl 379
10.1 a counter 38o
10.2 a 4-bit multiplier 381
10.3 syntax and semantics of vhdl 390
10.4 identifiers and literals 392
10.5 entities and architectures 393
10.6 packages and libraries 398
10．7 interface deciarations 405
10．8 type deciartions 411
10．9 other declarations 413
10．10 sequential statements 419
10．11 operators 430
10．12 arithmetic 432
10．13 concurrent statements 437
10．14 execution 445
10．15 configurations and specifications 447
10．16 an engine controller 449
10．17 summary 456
10．18 problems 459
10．19 bibliography 477
10．20 references 478
11 verllog hdl 479
11．1 acounter 480
11. 2 basics of the verilog language 482
11．3 operators 490
11．4 hierchy 494
11．5 procedures and assignments 495
11．6 timing controis and deiay 498
11．7 tasks and functions 506
11．8 control statements 506
11．9 logic-gate modding 509
11．10 modeiing delay 512
11．11 aitering parameters 515
11．12 a viterbi decoder 515
11．13 other verilog features 532
11．14 summary 541
11．15 probiems 543
11．16 bibliography 557
11．17 references 557
12 logic synthesis 559
12．1 a logic-synthesis exampie 560
12．2 a comparator／mux 561
12．3 inside a logic synthesizer 569
12．4 synthesis of the viterbi decoder 572
12．5 verilog and logic synthesis 580
12．6 vhdl and loqic synthesis 593
12．7 finite—state machine synthesis 605
12．8 memory synthesis 611
12．9 the muitiplier 614
12．10 the engine controller 619
12．11 performance-driven synthesis 620
12．12 optimization of the viterbi decoder 625
12．13 summary 628
12．14 probiems 629
12．15 bibiiography 638
12．16 references 639
13 simulation 641
13．1 types of simuiation 641
13．2 the comparator／mux exampie 643
13．3 logic systems 652
13．4 how logic simuiation works 656
13．5 cell modeis 659
13．6 delay models 669
13．7 static timing anaiysis 675
13．8 formal verification 682
13．9 switch-level simulation 688
13．10 transistor—levei simuiation 689
13．11 summary 696
13．12 probiems 696
13．13 bibliography 708
13．14 referellces 708
14 test 711
14．1 the lmportance of test 712
14．2 boundary-scan test 714
14．3 fauits 736
14．4 fauit simuiation 745
14．5 automatic test-pattern generation 755
14．6 scan test 764
14. 7 built—in seif—test 766
14．8 a simpie test example 778
14．9 the viterbi decoder example 791
14．10 summary 794
14．11 problems 794
14．12 bibiiography 800
14．13 references 801
15 asic construction 805
15．1 physical design 805
15．2 cad tools 807
15．3 system partitioning 809
15．4 estimating asic size 811
15．5 power dissipation 816
15. 6 fpga partitioning 820
15．7 partitioning methods 824
15．8 summary 838
15．9 probiems 838
15．10 bibiiography 850
15．11 references 851
16 floorplannlng
and placement 853
16．1 floorplanning 853
16．2 piacement 873
16．3 physical design flow 894
16．4 information formats 895
16．5 summary 898
16．6 probiems 898
16．7 bibiiography 906
16．8 references 906
17 routlng 909
17．1 giobal routing 910
17．2 detailed routing 922
17．3 special routing 935
17．4 circuit extraction and drc 939
17.5 summary 946
1 7.6 problems 947
1 7.7 bibliography 956
1 7.8 references 957
a vhdl resources 961
1.1 bnf 961
1 .2 vhdl syntax 963
1 .3 bnf index 979
1 .4 bibliography 973
1 .5 references 976
b verilog hdl
resources 979
2.1 explanation of the verilog hdl bnf 979
2.2 verilog hdl syntax 980
2.3 bnf index 994
2.4 verilog hdl lrm 994
2.5 bibliography 997
2.6 references 999
glossary 1000
index 1006
1 .1 types of asics 4
1 .2 design flow 16
1 .3 case study 18
1 .4 economics of asics 20
1 .5 asic cell libraries 27
1 .6 summary 30
1 .7 problems 31
1 .8 bibliography 36
1 .9 references 38
2 cmos logic 39
2.1 cmos transistors 41
2.2 the cmos process 49
2.3 cmos design rules 58
2.4 combinational logic cells 60
2.5 sequential logic cells 70
2.6 datapath logic cells 75
2.7 i/o cells 99
2.8 cell compilers 102
2.9 summary 102
. 2.10 problems 103
2.11 bibliography 113
2.12 references 1 14
3 asic library design 117
3.1 transistors as resistors 117
3.2 transistor parasitic capacitance 122
3.3 logical effort 129
9.4 library-cell design 141
9.5 library architecture 142
3.6 gate-array design 144
3.7 standard-cell design 150
3.8 datapath-cell design 152
3.9 summary 155
3.10 problems 155
3.11 bibliography 187
3.12 references 168
4 programmable asics 169
4.1 the antifuse 170
4.2 static ram 1 74
4.3 eprom and eeprom technology 174
4.4 praaical isues 1 7e
4.5 specifications 1 7b
4.6 prep benchmarks 1 79
4.7 fpga economics 1 80
4.8 summary 184
4.9 problems 185
4.10 bibliography 190
4.11 references 190
5 programmable asic
logic cells 191
5.1 actel act 191
5.2 xilinx lca 204
5.3 altera flex 209
5.4 altera max 209
5.5 summary 218
5.6 problems 224
5.7 bibliography 229
5.8 references 230
6 programmable
asic i/o cells 231
6.1 dc output 292
6.2 ac output 295
8.9 dc input 243
6.4 ac input 24b
6.5 clock input 253
6.6 power input 255
6.7 xilinx i/o block 258
6.8 other i/o cells 261
6.9 summary 262
e.10 problems 269
6.11 bibliography 272
6.12 references 273
7 programmable
asic interconnect 275
7.1 aael act 275
7.2 xilinx lca 284
7.s xilinx epld 288
7.4 altera max 5000 and 7000 289
7.5 altera max 9000 290
7.6 altera flex 291
7.7 summary 292
7.8 problems 294
7.9 bibliography 297
7.10 references 297
8 programmable
asic design software 299
8.1 desian svstems 299
8.2 logic synthesis 3o4
8.3 the halfgate asic 307
8.4 summary 316
8.5 probiems 316
8.6 bibliography 320
8.7 references 326
9 low-level
design entry 327
9.1 schematic entry 328
9.2 low-level design languages 345
9.3 pla tools 353
9.4 edif 355
9.5 cfi design representation 969
9.6 summary 373
9.7 problems 373
9.8 bibliography 376
9.9 references 377
10 vhdl 379
10.1 a counter 38o
10.2 a 4-bit multiplier 381
10.3 syntax and semantics of vhdl 390
10.4 identifiers and literals 392
10.5 entities and architectures 393
10.6 packages and libraries 398
10．7 interface deciarations 405
10．8 type deciartions 411
10．9 other declarations 413
10．10 sequential statements 419
10．11 operators 430
10．12 arithmetic 432
10．13 concurrent statements 437
10．14 execution 445
10．15 configurations and specifications 447
10．16 an engine controller 449
10．17 summary 456
10．18 problems 459
10．19 bibliography 477
10．20 references 478
11 verllog hdl 479
11．1 acounter 480
11. 2 basics of the verilog language 482
11．3 operators 490
11．4 hierchy 494
11．5 procedures and assignments 495
11．6 timing controis and deiay 498
11．7 tasks and functions 506
11．8 control statements 506
11．9 logic-gate modding 509
11．10 modeiing delay 512
11．11 aitering parameters 515
11．12 a viterbi decoder 515
11．13 other verilog features 532
11．14 summary 541
11．15 probiems 543
11．16 bibliography 557
11．17 references 557
12 logic synthesis 559
12．1 a logic-synthesis exampie 560
12．2 a comparator／mux 561
12．3 inside a logic synthesizer 569
12．4 synthesis of the viterbi decoder 572
12．5 verilog and logic synthesis 580
12．6 vhdl and loqic synthesis 593
12．7 finite—state machine synthesis 605
12．8 memory synthesis 611
12．9 the muitiplier 614
12．10 the engine controller 619
12．11 performance-driven synthesis 620
12．12 optimization of the viterbi decoder 625
12．13 summary 628
12．14 probiems 629
12．15 bibiiography 638
12．16 references 639
13 simulation 641
13．1 types of simuiation 641
13．2 the comparator／mux exampie 643
13．3 logic systems 652
13．4 how logic simuiation works 656
13．5 cell modeis 659
13．6 delay models 669
13．7 static timing anaiysis 675
13．8 formal verification 682
13．9 switch-level simulation 688
13．10 transistor—levei simuiation 689
13．11 summary 696
13．12 probiems 696
13．13 bibliography 708
13．14 referellces 708
14 test 711
14．1 the lmportance of test 712
14．2 boundary-scan test 714
14．3 fauits 736
14．4 fauit simuiation 745
14．5 automatic test-pattern generation 755
14．6 scan test 764
14. 7 built—in seif—test 766
14．8 a simpie test example 778
14．9 the viterbi decoder example 791
14．10 summary 794
14．11 problems 794
14．12 bibiiography 800
14．13 references 801
15 asic construction 805
15．1 physical design 805
15．2 cad tools 807
15．3 system partitioning 809
15．4 estimating asic size 811
15．5 power dissipation 816
15. 6 fpga partitioning 820
15．7 partitioning methods 824
15．8 summary 838
15．9 probiems 838
15．10 bibiiography 850
15．11 references 851
16 floorplannlng
and placement 853
16．1 floorplanning 853
16．2 piacement 873
16．3 physical design flow 894
16．4 information formats 895
16．5 summary 898
16．6 probiems 898
16．7 bibiiography 906
16．8 references 906
17 routlng 909
17．1 giobal routing 910
17．2 detailed routing 922
17．3 special routing 935
17．4 circuit extraction and drc 939
17.5 summary 946
1 7.6 problems 947
1 7.7 bibliography 956
1 7.8 references 957
a vhdl resources 961
1.1 bnf 961
1 .2 vhdl syntax 963
1 .3 bnf index 979
1 .4 bibliography 973
1 .5 references 976
b verilog hdl
resources 979
2.1 explanation of the verilog hdl bnf 979
2.2 verilog hdl syntax 980
2.3 bnf index 994
2.4 verilog hdl lrm 994
2.5 bibliography 997
2.6 references 999
glossary 1000
index 1006
Application-Specific Integrated Circuits
- 名称
- 类型
- 大小
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