Preface 5
This Book and Simulation Software Bundle Project 5
Subject and Purpose of This Book 6
The Book Structure 7
Acknowledgments 10
Contents 12
1 Introduction 18
1.1 Analog and Digital in Prism of ESD Design 18
1.2 Important Definitions 21
1.2.1 ESD Protection Network 21
1.2.2 ESD Clamps 23
1.2.3 Absolute Maximum Limits and Pulsed SOA 24
1.2.4 ESD Pulse Specification 25
1.2.5 Breakdown and Instability 26
DECIMM TM Simulation Examples for Introduction 31
2 Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection 32
2.1 Important Definitions and Limitations 32
2.1.1 Basic Semiconductor Structures 32
2.1.2 Conductivity Modulation and Negative Differential Resistance 34
2.1.3 Spatial Current Instability, Filamentation, and Suppression 35
2.1.4 Snapback Operation 37
2.1.5 Notes to the Methodology of Material Presentation in This Chapter 39
2.2 Avalanche Breakdown in Reverse-Biased pn Structure 40
2.2.1 Analytical Description of the Avalanche Breakdown Phenomenon 41
2.2.2 Numerical Analysis of the Avalanche Breakdown in the p+\u2013p\u2013n+Structure 43
2.3 Double-AvalancheInjection in pin Structures 47
2.3.1 An Analytical Description of the Effect 47
2.3.2 Numerical Analysis for the p\u2013i\u2013n Diode Structure 48
2.4 AvalancheInjection in Si n+\u2013n\u2013n+ Diode Structure 50
2.4.1 Analytical Approach 51
2.4.2 Simulation Analysis 53
2.5 Conductivity Modulation Instability in npn Diode Structures 54
2.5.1 Conductivity Modulation in a Floating Base Region: Diode Operation Mode 54
2.5.1.1 The Case of Floating Base Breakdown (BVCEO) IB=0 54
2.5.1.2 Numerical Solution for IB=0 Case 56
2.6 Conductivity Modulation in the Triode npn Structure 57
2.6.1 The Case of Grounded Base Breakdown Operation UEB = 0 (BVCES) 57
2.6.2 The Floating Emitter Case IE=0 58
2.6.3 Avalanche-Injection in a Common Emitter Circuit: The Case of I B< 0 Regime 58
2.6.3.1 Numerical Analysis for IB < 0 Case 61
2.6.4 Avalanche-Injection in the Common Emitter Circuit with Positive Base Current IB> 0 64
2.6.4.1 Analytical Description of the IB > 0 Case 65
2.6.4.2 Numerical Analysis of the IB > 0 Case 66
2.6.5 Avalanche--Injection in the Common Base Circuit 68
2.7 AvalancheInjection in PNP Structures 69
2.8 Double Injection in Si pnpn Structures 70
2.8.1 Equivalent Circuit 70
2.8.2 Simulation of Conductivity Modulation in p--n--p--n Structures 73
2.8.2.1 Floating Base Case 73
2.8.2.2 Connected Base Case 75
2.9 Spatial Current Instability Phenomena in Semiconductor Structures with Negative Differential Resistance 76
2.9.1 Current Filamentation at Avalanche--Injection 77
2.9.2 Current Filamentation Effect in Double-Avalanche--Injection Conductivity Modulation 80
2.9.3 Current Filamentation Effect in the Case of Double Injection 83
2.10 Summary 83
DECIMM TM Simulation Examples for Chapter 2 85
3 Standard and ESD Devices in Integrated Process Technologies 86
3.1 ESD Specifics in Integrated Process Technology 87
3.1.1 Typical DGO CMOS Process with Extended Voltage Components 87
3.1.1.1 Initial Wafer Material 88
3.1.1.2 Device Isolation 89
3.1.1.3 Deep Nwell isolation 90
3.1.1.4 Well Implants 92
3.1.1.5 Gate Oxide 93
3.1.1.6 Polygate 93
3.1.1.7 Lightly Doped Drain Implants 95
3.1.1.8 Spacer Formation and NPLUS and PPLUS Implants 96
3.1.1.9 Activation and Silicidation 97
3.1.1.10 Contacts and Backend 99
3.1.2 ESD Specific for BCD and BiCMOS Integrated Process Flow 100
3.1.2.1 Generic Process Flow 100
3.1.2.2 Subcollector and Substrate Isolation Regions 101
3.1.2.3 Isolation BCD Process Steps 103
3.1.2.4 Collector and Initial CMOS Regions 103
3.2 Safe Operating Area in ESD Pulse Regime 104
3.2.1 SOA and Current Instability Boundary in Reliability 105
3.2.2 Pulsed SOA for ESD Regimes 107
3.2.2.1 Standard Devices 108
3.2.3 ESD SOA for Typical Devices in BCD Process 109
3.2.3.1 Waveform SOA Measurements 112
3.2.4 Instability Boundary and SOA for ESD devices 113
3.2.5 Physical Limitation of ESD Devices. Spatial Thermal Runaway 115
3.3 Low-Voltage ESD Devices in CMOS Processes 119
3.3.1 Snapback NMOS 120
3.3.1.1 Three-Dimensional Simulation of Current Instability in Snapback NMOS Devices 121
3.3.2 FOX (TFO) ESD device 122
3.3.2.1 Surface NPN 124
3.3.3 LVTSCR and FOXSCR 126
3.3.4 Low-Voltage Avalanche Diodes 128
3.3.4.1 Comparison of the Surface and Buried Avalanche Diodes 129
3.4 ESD Devices in BJT Processes 129
3.4.1 Integrated NPN BJT Devices 131
3.4.2 Bipolar SCR 133
3.5 High-Voltage ESD Devices in BCD and Extended Voltage CMOS Processes 134
3.5.1 LDMOS-SCR and DeMOS-SCR Devices 135
3.5.2 Lateral PNP BJT Devices 138
3.5.3 High-Voltage Avalanche Diodes 143
3.6 Dual Direction Devices 144
3.6.1 Dual-Direction Device Architecture in CMOS Process 145
3.6.1.1 Device-Level Positive and Negative Feedback 146
3.6.2 High-Voltage Dual-Direction Devices 148
3.6.3 Dual Direction ESD Devices Based upon Si--Ge NPN BJT Structure 151
3.6.3.1 Experimental Characteristics of the DD-BJT Clamp 154
3.7 ESD Diodes and Passive Components 156
3.7.1 Forward-Biased ESD Diodes 156
3.7.1.1 CMOS Diodes 157
3.7.1.2 Gated Diodes 158
3.7.2 Passives 159
3.7.2.1 Saturation Resistors 160
3.7.2.2 Thin Film Resistors 163
3.8 Summary 164
DECIMM TM Simulation Examples for Chapter 3 165
Example 3.1 Standard Devices in BCD Process Technology 166
Example 3.2 Typical ESD Devices in 0.5 m BCD Process Technology 167
Example 3.3 Ring Oscillators 170
4 ESD Clamps 172
4.1 Active NMOS Clamp 175
4.2 Low-Voltage Clamps with Internal Blocking Junction Reference or dV/dt Turn-on 178
4.2.1 Snapback NMOS Clamps 178
4.2.1.1 Ground-Referenced Snapback NMOS 178
4.2.1.2 Gate Coupling 178
4.2.1.3 Displacement Current Effect 179
4.2.1.4 Reverse Path Protection 181
4.2.1.5 Isolated Snapback NMOS 181
4.2.1.6 The 40 Rule for Backend 183
4.2.2 Transient-Triggered PMOS Clamp 184
4.2.3 10V FOX Snapback Device 186
4.2.4 LVTSCR and FOX-SCR Clamps 188
4.2.5 High Holding Voltage LVTSCR Clamps 189
4.2.5.1 High Holding Voltage Cell Topology 189
4.2.5.2 Clamp-Level High Holding Voltage Using P-Emitter De-biasing 191
4.2.6 Triggering Characteristics Control in SCR Clamps 193
4.2.6.1 Mixed Device-Circuit Concept 194
4.2.6.2 Practical Implementation of the Concept for the Case of 130 nm Process 194
4.2.6.3 Principle of Dual-Base Control Operation 195
4.2.6.4 Pulsed Characterization of Dual-Base Control (DBC) Clamp 197
4.2.6.5 DC Leakage of DBC Clamp 198
4.3 Voltage and Current Reference in ESD Clamp 199
4.3.1 Low-Voltage Clamps in BiCMOS process technology 200
4.3.2 NPN Clamps with Voltage Reference 202
4.4 High-Voltage ESD Devices 205
4.4.1 20 V NPN with Blocking Junction Internal Reference 206
4.4.2 NPN Clamp with External Lateral Avalanche Diode Reference 207
4.4.3 SCR-Based High-Voltage Clamp 207
4.4.4 Lateral LPNP Clamp 207
4.4.5 Mixed Device-Circuit Dual Mode Solutions 208
4.4.5.1 Example of Circuit Design 209
4.5 The Concept of Self-Protection 213
4.5.1 Device-Level Self-Protection 213
4.5.2 Array-Level Protection 215
4.6 ESD Protection of Ultra High Voltage Circuits 217
4.7 Summary 220
DECIMMTM Simulation Examples for Chapter 4 221
Example 4.1 Snapback NMOS Clamp Operation Analysis 221
Example 4.2 LVTSCR ESD Clamps 222
Example 4.3 Two-Stage ESD Protection with Snapback NMOS 223
Example 4.4 High-Voltage NLDMOS-SCR Clamp with High-Side Avalanche Diode Reference 224
Example 4.5 PNP Clamp with Low Side Avalanche Diode Reference 225
Example 4.6 High-Voltage NPN Clamp 226
Example 4.7 Bipolar SCR ESD Clamp 227
Example 4.8 Diode-Triggered SCR ESD Clamp 228
5 ESD Network Design Principles 230
5.1 Rail-Based ESD Protection Network 232
5.1.1 Rail Based and Local ESD Protection 232
5.1.2 Rail-Based ESD Protection Using Snapback Clamps 234
5.1.3 Rail-Based ESD Protection Using Active Clamps 236
5.1.4 Specific of Active Clamp Design in BiCMOS Processes 240
5.1.4.1 Verification by Circuit Simulation 240
5.1.4.2 Experimental Comparison 242
5.1.4.3 Active Clamp Protection in Complementary BiCMOS with Low-Voltage CMOS Components 244
5.1.5 Bipolar Differential Input Protection 249
5.1.6 Bipolar Output Protection 251
5.1.7 CMOS Input and Output Protection 252
5.1.8 Array-Level Consideration 254
5.1.9 Concept of Two-Stage Protection 257
5.1.9.1 CMOS Input 257
5.1.9.2 Diode-Based Compact Two-Stage ESD Protection Circuit 258
5.1.9.3 Two-Stage ESD Protection Circuit for BJT Base 260
5.1.9.4 Two-Stage Network with Snapback NMOS 261
5.2 Local Clamp-Based ESD Protection Network 264
5.2.1 Local ESD Protection 264
5.2.2 Serial Data Line Pin Case Study 265
5.2.3 Erase Pin Protection in EEPROM 267
5.2.4 Local Protection of the Internal Pins 270
5.2.5 Local Protection of the High-Speed I/O pins 273
5.3 ESD Network for Multiple Voltage Domains 275
5.3.1 Multiple Voltage Domains 275
5.3.2 Protection of Multiple Voltage Domains with Single Active Clamp Network 277
5.3.3 Local Bi-directional ESD Protection of Differential Input 278
5.4 ESD Network Simulation with ESD Compact Models 280
5.4.1 Compact Model for Snapback NMOS and PMOS Devices 280
5.4.2 Snapback LVTSCR Model 282
5.4.3 Extended Voltage Snapback Compact Models 282
5.4.4 High-Voltage Open Drain Circuit Analysis 287
5.5 Summary 289
DECIMM TM Simulation Examples for Chapter 5 289
Example 5.1 Active 5 V NMOS Clamp 289
Example 5.2 Active 5 V PMOS Clamp 290
Example 5.3 EEPROM Erase pin Protection 291
Example 5.4 BJT-Based Active Clamps 292
Example 5.5 Stacked Active Clamps for High Voltage Tolerance 294
Example 5.6 Stacked Active Clamps with NPN 295
Example 5.7 Stacked Active Clamps with PNP 296
6 ESD Design for Signal Path Analog 297
6.1 Amplifiers 298
6.1.1 Amplifier Product Families and Specifications 298
6.1.2 ESD Solutions for Amplifiers 304
6.1.3 Bipolar Output High-Voltage Audio Amplifiers 306
6.1.4 Bipolar Output Protection in Low-Voltage Amplifiers 308
6.1.5 Input Protection 309
6.1.6 CMOS Output 311
6.2 Digital-to-Analog and Analog-to-Digital Converters 312
6.2.1 Functional Blocks for High-Speed DAC 313
6.2.1.1 ESD Protection Network 315
6.3 High-Speed Interface IO pins 317
6.3.1 Interface Analog Products 317
6.3.2 Cable Discharge Event Test Procedure for Integrated Circuits 318
6.3.3 ESD Protection of Interface Pins with CDE Requirements 321
6.4 Summary 323
DECIMMTM Simulation Examples for Chapter 6 323
Example 6.1a 6.1c Rail-Based Protection with Active 5 V NMOS Clamp and ESD Diodes 324
Example 6.2 Rail-Based Protection with 5 V Snapback NMOS Clamp and ESD Diodes 326
Example 6.3 Trans Impedance Amplifier 328
Example 6.4 CMOS Output Stage ESD Case 328
Example 6.5 CMOS Open Drain Case 329
Example 6.6 BJT Output Stage Case 330
7 Power Management Circuits ESD Protection 332
7.1 Power Management Products 333
7.1.1 Power Management Products and ESD Challenges 333
7.1.1.1 Market Trends 333
7.1.1.2 ESD Challenges 334
7.1.2 Integrated DC--DC Converters and Controllers 336
7.1.3 Integrated Power Arrays 338
7.1.3.1 Power Losses 338
7.1.3.2 Self-Protection Capability (SPC) of Integrated Power Arrays 343
7.1.3.3 Physical Simulation of DeMOS Power Arrays in ESD Regime 349
7.2 Low-Voltage Power Circuit ESD Cases 353
7.2.1 LV Power Switching Blocks 353
7.2.2 Step-Down DC--DC Converters 355
7.2.3 Local Snapback Protection of LV Switch Pin 358
7.2.3.1 Case Study 358
7.2.3.2 Mixed-Mode Simulation 360
7.3 ESD Protection of Integrated High-Voltage Regulators 362
7.3.1 Asynchronous Integrated Buck Regulator Case 362
7.3.1.1 Functionality and ESD Protection 362
7.3.1.2 Case Study 364
7.3.2 Synchronous Regulators 366
7.3.2.1 HV Power Train Block 366
7.3.2.2 Synchronous Buck Regulator 368
7.4 Controllers 372
7.4.1 Asynchronous Buck-Boost (SEPIC) Controller 374
7.4.2 Synchronous Buck Controller 377
7.5 Light Management Units and LED Drivers 379
7.5.1 Analog LED Technology 379
7.5.2 LED Drivers 381
7.5.3 Light Management Units 382
7.5.3.1 Switch Pin Protection 385
7.5.3.2 Feedback Pin Protection 385
7.5.3.3 LED Driver Protection 386
7.5.3.4 Gate Clamp 387
7.5.3.5 RGB Driver 387
7.5.3.6 Control Pins 388
7.5.3.7 Current Sink Protection 389
7.6 A Few More Case Studies 389
7.6.1 Power Array--ESD Clamp Interaction 389
7.6.2 Nepi--Nepi Transient Latch-Up Scenario 392
7.6.3 CDM Case of the High-Voltage Pin Protection 395
7.7 Summary 398
DECIMMTM Simulation Examples for Chapter 7 402
Example 7.1 Output Stage of Buck DC--DC Voltage Regulator 402
Example 7.2 5--V Boost DC--DC Converter and Transient Latch-Up 403
Example 7.3 High-Voltage Boost Output Stage 404
Example 7.4 100 600 V Boost Output Stage with Vertical DMOS and IGBT 405
Example 7.5 Power Array with Gate Clamp Example 405
Example 7.6 Serial Data Line Pin Case 406
8 System-Level and Discrete Components ESD 409
8.1 System-Level Specifications and Standards 410
8.1.1 Meaning of ESD Robust System 410
8.1.1.1 CE Mark 411
8.1.1.2 Basic EMC Standards 411
8.1.1.3 Automotive Industry Standards 411
8.1.1.4 IC and System-Level Comparison 412
8.1.2 System-Level ESD Pulse and Model 414
8.1.2.1 System-Level ESD Test for ICs 414
8.1.2.2 IEC ESD Pulse Waveforms 414
8.1.2.3 System-Level Test Setup 417
8.1.2.4 Cable Discharge Event (CDE) 418
8.1.3 Transient Latch-up During a System-Level Event 419
8.1.4 System-Level Protection Components 422
8.2 On-Wafer Human Metal Model Measurements 423
8.2.1 On-Wafer HMM Tester and Equivalent Circuit of the Pulse 424
8.2.1.1 Equivalent Circuit for HMM Simulation 425
8.2.2 HMM-HBM Component Correlation 426
8.2.2.1 Diodes Under HMM Stress 428
8.2.2.2 LVTSCR 428
8.2.2.3 High-Voltage ESD Clamps 429
8.3 On-Chip Design for System-Level Pins 430
8.3.1 Examples of Circuits with System-Level Protection 430
8.3.1.1 On-Chip and Suppressor ESD Device Interaction 435
8.4 Hot Swap and Hot Plug-in 436
8.4.1 The Concept of Two-Stage SCR ESD Devices 436
8.5 System-on-Package (SOP) Protection 442
8.6 ESD Robustness of Discrete Components 443
8.6.1 Discrete Components in High Reliability Systems 443
8.6.2 ESD Requirement for Discrete Components 443
8.6.2.1 ESD Effects on Power Transistors 444
8.6.2.2 Statistical Approach for ESD and Reliability Parameters Verification 445
8.6.3 Preliminary Numerical Analysis for Devices with Defects and the Two-Transistor Model 446
8.6.4 Experimental Evaluation of Discrete Components Robustness 450
8.6.4.1 TLP Stress 451
8.6.4.2 ISO System-Level Pulse Test 452
8.6.4.3 Collector--Emitter ISO Test 453
8.6.4.4 Gate--Collector ISO Tests 455
8.7 Summary 456
DECIMM TM Simulation Examples for Chapter 8 457
Example 8.1 System HMM Pulse Simulation 457
Example 8.2 HMM Simulation with PCB Components and TVS 457
Example 8.3 Power Switch 457
References 461
Index 469